By Shuvra S. Bhattacharyya (Editor), Ed F. Deprettere (Editor), Jurgen Teich (Editor), Ed Deprettere (E
Starting from low-level software and structure optimizations to high-level modeling and exploration matters, this authoritative reference compiles crucial study on numerous degrees of abstraction showing in embedded structures and software program layout. It promotes platform-based layout for better procedure implementation and modeling and more desirable functionality and value analyses. Domain-Specific Processors depends notions of concurrency and parallelism to meet functionality and price constraints because of more and more complicated functions and architectures and addresses innovations in specification, simulation, and verification in embedded structures and software program layout.
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Additional info for Domain-Specific Processors (Signal Processing and Communications, 20)
1a). In this representation the input signal is processed by several ( J) levels of decomposition (octaves), where the input at every stage is processed by a low-pass and by a high-pass ﬁlter, outputs of which are then downsampled by a factor of two. The length of the processed signal is twice reduced from level to level. Based on this representation of DWTs several low-hardware complexity devices have been developed that 41 42 Guevorkian et al. Figure 1 (a) Tree-structured ﬂowgraph representation of a 1-D DWT; (b) lifting step.
Our program can be embedded in higher level computations of various kind, implying variables or memories. Data descriptions are inferred from these levels. The resulting circuit is highly dependent from the data it is intended to process. An execution is the traversal of a hierarchical network of lookup tables in which values are forwarded. A value change in the input of a table implies a possible change in its output that in turn induces other changes downstream. These networks reﬂect the eﬀective function structure at the procedure call grain and they have a strong algorithmic meaning.
The highest throughput achieved in known architectures is N/2 clock cycles per N-point DWT (see ). Similar performance is achieved in highly (about 100%) eﬃcient architectures developed in [27–28] by including approximately twice the lower number of PEs from stage to stage. In [29–30], ﬂowgraph representation of DWTs (see examples in Figs. 2 and 3) has been suggested as a useful tool in designing parallel/pipelined DWT architectures. In particular, this representation fully reveals parallelism Figure 2 Flowgraph representation of a DWT (N=16, L=4, J=3).